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PALC22V10D Datasheet(PDF) 6 Page - Cypress Semiconductor

Part No. PALC22V10D
Description  FLASG ERASABLE REPROGRAMMABLE CMOS PAL DEVICE
Download  11 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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PALC22V10D Datasheet(HTML) 6 Page - Cypress Semiconductor

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PALC22V10D
6
Military and Industrial Switching Characteristics PALC22V10D[2, 7]
22V10D-10
22V10D-15
22V10D-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPD
Input to Output
Propagation Delay[8, 9]
3
10
3
15
3
25
ns
tEA
Input to Output Enable Delay[10]
10
15
25
ns
tER
Input to Output Disable Delay[11]
10
15
25
ns
tCO
Clock to Output Delay[8, 9]
2
7
2
8
2
15
ns
tS1
Input or Feedback SetUp Time
6
10
18
ns
tS2
Synchronous Preset SetUp Time
7
10
18
ns
tH
Input Hold Time
0
0
0
ns
tP
External Clock Period (tCO + tS)
12
20
33
ns
tWH
Clock Width HIGH[6]
3
6
14
ns
tWL
Clock Width LOW[6]
3
6
14
ns
fMAX1
External Maximum Frequency
(1/(tCO + tS))[12]
76.9
50.0
30.3
MHz
fMAX2
Data Path Maximum Frequency
(1/(tWH + tWL))[6, 13]
142
83.3
35.7
MHz
fMAX3
Internal Feedback Maximum
Frequency (1/(tCF + tS))[6,14]
111
68.9
32.2
MHz
tCF
Register Clock to
Feedback Input[6,15]
3
4.5
13
ns
tAW
Asynchronous Reset Width
10
15
25
ns
tAR
Asynchronous Reset
Recovery Time
6
12
25
ns
tAP
Asynchronous Reset to
Registered Output Delay
12
20
25
ns
tSPR
Synchronous Preset
Recovery Time
8
20
25
ns
tPR
PowerUp Reset Time[6,16]
1
1
1
ms


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