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PALC22V10D Datasheet(PDF) 5 Page - Cypress Semiconductor

Part No. PALC22V10D
Description  FLASG ERASABLE REPROGRAMMABLE CMOS PAL DEVICE
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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PALC22V10D Datasheet(HTML) 5 Page - Cypress Semiconductor

 
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PALC22V10D
5
Commercial Switching Characteristics PALC22V10D[2, 7]
22V10D-7
22V10D-10
22V10D-15
22V10D-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPD
Input to Output
Propagation Delay[8, 9]
3
7.5
3
10
3
15
3
25
ns
tEA
Input to Output Enable Delay[10]
8
10
15
25
ns
tER
Input to Output Disable Delay[11]
8
10
15
25
ns
tCO
Clock to Output Delay[8, 9]
2
5
2
7
2
8
2
15
ns
tS1
Input or Feedback SetUp Time
5
6
10
15
ns
tS2
Synchronous Preset SetUp Time
6
7
10
15
ns
tH
Input Hold Time
0
0
0
0
ns
tP
External Clock Period (tCO + tS)
10
12
20
30
ns
tWH
Clock Width HIGH[6]
3
3
6
13
ns
tWL
Clock Width LOW[6]
3
3
6
13
ns
fMAX1
External Maximum Frequency
(1/(tCO + tS))[12]
100
76.9
55.5
33.3
MHz
fMAX2
Data Path Maximum Frequency
(1/(tWH + tWL))[6, 13]
166
142
83.3
35.7
MHz
fMAX3
Internal Feedback Maximum
Frequency (1/(tCF + tS))[6,14]
133
111
68.9
38.5
MHz
tCF
Register Clock to
Feedback Input[6, 15]
2.5
3
4.5
13
ns
tAW
Asynchronous Reset Width
8
10
15
25
ns
tAR
AsynchronousResetRecoveryTime
5
6
10
25
ns
tAP
Asynchronous Reset to
Registered Output Delay
12
13
20
25
ns
tSPR
Synchronous Preset Recovery Time
6
8
10
15
ns
tPR
PowerUp Reset Time[6,16]
1
1
1
1
ms
Notes:
7. Part (a) of AC Test Loads and Waveforms is used for all parameters ex
cept tER and tEA(+). Part (b) of AC Test Loads and Waveforms is used
for tER. Part (c) of AC Test Loads and Waveforms is used for tEA(+).
8. Min. times are tested initially and after any design or process changes
that may affect these parameters.
9. This specification is guaranteed for all device outputs changing state in
a given access cycle.
10. The test load of part (a) of AC Test Loads and Waveforms is used for
measuring tEA(-). The test load of part (c) of AC Test Loads and
Waveforms isusedformeasuringtEA(+)only.Pleaseseepart(e)ofAC
Test Loads and Waveforms for enable and disable test waveforms and
measurement reference levels.
11. This parameter is measured as the time after output disable input that
the previous output data state remains stable on the output. This delay
is measured to the point at which a previous HIGH level has fallen to
0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts
above VOL max. Please see part (e) of AC Test Loads and Waveforms
for enable and disable test waveforms and measurement reference
levels.
12. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with external feedback can
operate.
13. This specification indicates the guaranteed maximum frequency at
which the device can operate in data path mode.
14. This specification indicates the guaranteed maximum frequency at
which a state machine configuration with internal only feedback can
operate.
15. This parameter is calculated from the clock period at fMAX internal
(1/fMAX3) as measured (see Note 11 above) minus tS.
16. The registers in the PALC22V10D have been designed with the capa
bility to reset during system powerup. Following powerup, all regis
ters will be reset to a logic LOW state. The output state will depend on
the polarity of the output buffer. This feature is useful in establishing
statemachineinitialization.Toinsureproperoperation,theriseinVCC
must be monotonic and the timing constraints depicted in PowerUp
Reset Waveform must be satisfied.


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