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PCF85116-3T Datasheet(PDF) 11 Page - NXP Semiconductors |
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PCF85116-3T Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 1997 Apr 02 11 Philips Semiconductors Product specification 2048 × 8-bit CMOS EEPROM with I2C-bus interface PCF85116-3 Note 1. The bus capacitance ranges from 10 to 400 pF (Cb = total capacitance of one bus line in pF). 11 I2C-BUS CHARACTERISTICS All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing from VSS to VDD. Notes 1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by a transmitter. 2. Cb = total capacitance of one bus line in pF. SCL input (pin 6) VIL LOW level input voltage −0.8 +0.3VDD V VIH HIGH level input voltage 0.7VDD 6.5 V ILI input leakage current VI =VDD or VSS −±1 µA fSCL clock input frequency 0 400 kHz tSP pulse width of spikes suppressed by filter 0 100 ns CI input capacitance VI =VSS − 7pF WP input (pin 7) VIL LOW level input voltage −0.8 +0.1VDD V VIH HIGH level input voltage 0.9VDD VDD + 0.8 V Data retention time tS data retention time Tamb =55 °C20 − years SYMBOL PARAMETER CONDITIONS STANDARD MODE FAST MODE UNIT MIN. MAX. MIN. MAX. fSCL clock frequency 0 100 0 400 kHz tBUF time the bus must be free before new transmission can start 4.7 − 1.3 −µs tHD;STA START condition hold time after which first clock pulse is generated 4.0 − 0.6 −µs tLOW LOW level clock period 4.7 − 1.3 −µs tHIGH HIGH level clock period 4.0 − 0.6 −µs tSU; STA set-up time for START condition repeated start 4.7 − 0.6 −µs tHD; DAT data hold time for CBUS compatible masters 5 −− −µs for I2C-bus devices note 1 0 − 0 − ns tSU; DAT data set-up time 250 − 100 − ns tr SDA and SCL rise time − 1000 20 + 0.1Cb(2) 300 ns tf SDA and SCL fall time − 300 20 + 0.1Cb(2) 300 ns tSU; STO set-up time for STOP condition 4.0 − 0.6 −µs SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT |
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