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XPC740P Datasheet(PDF) 3 Page - Motorola, Inc |
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XPC740P Datasheet(HTML) 3 Page - Motorola, Inc |
3 / 44 page MPC750A RISC Microprocessor Hardware Specifications 3 Overview 1.1 Overview The MPC750 is targeted for low-cost, low-power systems and supports the following power management features—doze, nap, sleep, and dynamic power management. The MPC750 consists of a processor core and an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus. Figure 1 shows a block diagram of the MPC750. Figure 1. MPC750 Block Diagram Completion Instruction Fetch Control Unit 32K ICache BHT/BTIC Dispatch System Unit Branch Unit FXU1 FXU2 GPRs Rename Buffers LSU FPU 32K DCache L2 Tags L2 Cache BIU FPRs Rename Buffers 60x BIU Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com AR CH IVE D B Y F RE ES CA LE SE MI CO ND UC TO R, INC . |
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