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LM5165QDRCTQ1 Datasheet(PDF) 4 Page - Texas Instruments |
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LM5165QDRCTQ1 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 47 page  SS ILIM RT PGOOD SW FB GND EN VIN HYS 1 2 3 4 5 10 9 8 7 6 SS ILIM RT PGOOD SW VOUT GND EN VIN HYS 1 2 3 4 5 10 9 8 7 6 LM5165X, LM5165Y Fixed Output Versions LM5165 Adjustable Output Version 4 LM5165-Q1 SNVSAJ3A – MARCH 2016 – REVISED MARCH 2016 www.ti.com Product Folder Links: LM5165-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) P = Power, G = Ground, I = Input, O = Output. 5 Pin Configuration and Functions DRC Package 10-Pin VSON with Exposed Thermal Pad Top View Pin Functions PIN I/O(1) DESCRIPTION NAME NO. SW 1 P Switching node that is internally connected to the drain of the high-side PMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Connect to the switching side of the power inductor. VIN 2 P Regulator supply input pin to high-side power MOSFET and internal bias rail LDO. Connect to input supply and input capacitor CIN. Path from VIN to the input capacitor must be as short as possible. ILIM 3 I Programming pin for current limit. Connecting the appropriate resistor from ILIM to GND selects one of four pre-set current limit options. Short ILIM to GND for the maximum current setting. SS 4 I Programming pin for the soft-start time. If a 100-k Ω resistor is connected from SS to GND, the internal soft- start circuit is disabled and the FB comparator reference steps immediately from zero to full value when the regulator is enabled by the EN input. If the SS pin is left open, the internal soft-start circuit ramps the FB reference from zero to full value in 900 µs. If an appropriate capacitance is connected to the SS pin, the soft-start time can be programmed as required. RT 5 I Mode selection and on-time programming pin for Constant On-Time (COT) control. Short RT to GND to select PFM (pulse frequency modulation) operation. Connect a resistor from RT to GND to program the on- time, which sets the switching frequency for COT. PGOOD 6 O Power Good output flag pin. PGOOD is connected to the drain of an NFET that holds the pin low when either FB or VOUT is below the regulation target. Use a pull-up resistor of 10 k Ω to 100 kΩ to the system voltage rail or VOUT (no higher than 12 V). EN 7 I Input pin of the precision enable / UVLO comparator. The converter is enabled when the EN voltage is greater than 1.212V. VOUT/FB 8 I Feedback input to voltage regulation loop. The VOUT pin connects the internal feedback resistor divider to the regulator output voltage for fixed 3.3V and 5V options. The FB pin connects the internal feedback comparator to an external resistor divider for the adjustable output voltage option. The FB comparator reference voltage is nominally 1.223V. HYS 9 O Drain of an internal NFET that is turned off when the EN input is greater than the EN threshold. An external resistor from HYS to the EN pin UVLO resistor divider programs the input UVLO hysteresis voltage. GND 10 G Regulator ground return. PAD - P Exposed pad. Connect to the GND pin and system ground on PCB. Path to CIN must be as short as possible. |
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