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LMK61E0M-SIAT Datasheet(PDF) 5 Page - Texas Instruments |
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LMK61E0M-SIAT Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 47 page  5 LMK61E0M www.ti.com SNAS692 – JANUARY 2017 Product Folder Links: LMK61E0M Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 3.3-V LVCMOS Output Characteristics (1) (continued) VDD = 3.3 V ± 5%, TA = –40°C to 85°C, outputs loaded with 2 pF to GND PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) Ensured by characterization. tR/tF (2) Output Rise/Fall Time 20% to 80%, R22[7:6] = 0x2 1.1 ns 20% to 80%, R22[7:6] = 0x0 0.2 ns PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) 70.656 MHz -150 dBc/Hz ODC(2) Output Duty Cycle Fast mode, R22[7:6] = 0x0 45% 55% ROUT Output Impedance 50 Ω 6.7 OE Input Characteristics VDD = 3.3 V ± 5%, TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH Input High Voltage 1.4 V VIL Input Low Voltage 0.6 V IIH Input High Current VIH = VDD -40 40 µA IIL Input Low Current VIL = GND -40 40 µA CIN Input Capacitance 2 pF 6.8 ADD Input Characteristics VDD = 3.3 V ± 5%, TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH Input High Voltage 1.4 V VIL Input Low Voltage 0.4 V IIH Input High Current VIH = VDD –40 40 µA IIL Input Low Current VIL = GND –40 40 µA CIN Input Capacitance 2 pF (1) Ensured by characterization. 6.9 Frequency Tolerance Characteristics (1) VDD = 3.3 V ± 5%, TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fT Total Frequency Tolerance All frequency bands and device junction temperature up to 120°C; includes initial freq tolerance, temperature & supply voltage variation, and 5 year aging at 40°C ambient temperature –25 25 ppm 6.10 Frequency Margining Characteristics VDD = 3.3 V ± 5%, TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fT Frequency Margining Range from Nominal –1000 1000 ppm |
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