Philips Semiconductors

Product specification

NE/SE564

Phase-locked loop

1994 Aug 31

8

6. If pulsed burst or ramp frequency is used for input signal, special

loop filter design may be required in place of simple single

capacitor filter on Pins 4 and 5. (See PLL application section)

7. The input signal to Pin 6 and the VCO feedback signal to Pin 3

must have a duty cycle of 50% for proper operation of the phase

detector. Due to the nature of a balanced mixer if signals are not

50% in duty cycle, DC offsets will occur in the loop which tend to

create an artificial or biased VCO.

8. For multiplier circuits where phase jitter is a problem, loop filter

capacitors may be increased to a value of 10 - 50

µF on Pins 4,

5. Also, careful supply decoupling may be necessary. This

1

2

6

7

3

9

11

4

5

10

15

16

14

12

13

8

+5V

BIAS

ADJ

2k

FSK

INPUT

1k

1k

+5V

300pF

300pF

HYSTERESIS

ADJUST

10k

2k

1.2k

FSK

OUTPUT

0–20pF

33pF

NE564

510

Ω

0.1

µF

10k

0.1

µF

0.22

µF 0.22µF

10

µF/8V

*510

Ω

*NOTE:

Use R9-11 only if rise time is critical.

SR01034

Figure 10. 10.8MHz FSK Decoder Using the 564