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PLUS405-37 Datasheet(PDF) 2 Page - NXP Semiconductors |
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PLUS405-37 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 20 page Philips Semiconductors Product specification PLUS405-37/-45 Programmable logic sequencers (16 × 64 × 8) 2 1996 Nov 12 853–1280 17500 DESCRIPTION The PLUS405 devices are bipolar, programmable state machines of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are connected to the 16 external dedicated inputs (I0 - I15) and to the feedback paths of the 8 on-chip State Registers (QP0 - QP7). Two complement arrays support complex IF-THEN-ELSE state transitions with a single product term (input variables C0, C1). All state transition terms can include True, False and Don’t Care states of the controlling state variables. All AND gates are merged into the programmable OR array to issue the next-state and next-output commands to their respective registers. Because the OR array is programmable, any one or all of the 64 transition terms can be connected to any or all of the State and Output Registers. All state (QP0 - QP7) and output (QF0 - QF7) registers are edge-triggered, clocked J-K flip-flops, with Asynchronous Preset and Reset options. The PLUS405 architecture provides the added flexibility of the J-K toggle function which is indeterminate on S-R flip-flops. Each register may be individually programmed such that a specific Preset-Reset pattern is initialized when the initialization pin is raised to a logic level “1”. This feature allows the state machine to be asynchronously initialized to known internal state and output conditions, prior to proceeding through a sequence of state transitions. Upon power-up, all registers are unconditionally preset to “1”. If desired, the initialization input pin (INIT) can be converted to an Output Enable (OE) function as an additional user-programmable feature. Availability of two user-programmable clocks allows the user to design two independently clocked state machine functions consisting of four state and four output bits each. Order codes are listed in the Ordering Information Table. FEATURES • PLUS405-37 – fMAX = 37MHz – 50MHz clock rate • PLUS405-45 – fMAX = 45MHz – 58.8MHz clock rate • Functional superset of PLS105/105A • Field-programmable (Ti-W fusible link) • 16 input variables • 8 output functions • 64 transition terms • 8-bit State Register • 8-bit Output Register • 2 transition Complement Arrays • Multiple clocks* • Programmable Asynchronous Initialization or Output Enable • Power-on preset of all registers to “1” • “On-chip” diagnostic test mode features for access to state and output registers • 950mW power dissipation (typ.) • TTL compatible • J-K or S-R flip-flop functions • Automatic “Hold” states • 3-State outputs APPLICATIONS • Interface protocols • Sequence detectors • Peripheral controllers • Timing generators • Sequential circuits • Elevator contollers • Security locking systems • Counters • Shift registers PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 N Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CLK I7 I6 I5/CLK I4 I3 I2 I1 I0 F7 F6 F5 F4 GND F3 F2 F1 F0 INIT/OE I15 I14 I13 I12 I11 I10 I9 I8 VCC CLK I6 I7 VCC I5/CLK I8 I9 I4 I3 I2 I1 I0 F7 F6 F5 F4 GND F3 F2 F1 F0 INIT/OE I15 I14 I13 I12 I11 I10 N = Plastic DIP (600mil-wide) A = Plastic Leaded Chip Carrier A Package SP00251 |
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