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61SP6464 Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc

Part # 61SP6464
Description  64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

61SP6464 Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. C
01/14/04
IS61SP6464
ISSI ®
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice.
ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
FEATURES
• Fast access time:
– 117, 100 MHz
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Five chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 128-Pin TQFP 14mm x 20mm
package
• Single +3.3V power supply
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VDDQ to alter their power-up state
DESCRIPTION
The
ISSI IS61SP6464 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-performance,
secondary cache for the i486™, Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 65,536 words
by 64 bits, fabricated with
ISSI's advanced CMOS technology.
The device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls I/O1-I/O8,
BW2 controls I/O9-I/O16, BW3 controls I/
O17-I/O24,
BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40,
BW6 controls I/O41-I/O48, BW7 controls I/O49-I/
O56,
BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on
GW input would cause all bytes to be written.
Bursts can be initiated with either
ADSP (Address Status
Processor) or
ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP6464 and controlled by the
ADV (burst address
advance) input pin.
Asynchronous signals include output enable (
OE), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates after
the wake-up period. A LOW input, i.e., GNDQ, on MODE pin
selects LINEAR Burst. A VDDQ (or no connect) on MODE pin
selects INTERLEAVED Burst.
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
JANUARY 2004


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