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61SP6464 Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc

Part # 61SP6464
Description  64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

61SP6464 Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc

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IS61SP6464
ISSI®
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
TRUTH TABLE
ADDRESS
OPERATION
USED
CE3
CE2
CE3
CE3
CE3
CE3
CE3
CE2
CE2
CE2
CE2
CE2
CE
CE
CE
CE
CE
ADSP
ADSP
ADSP
ADSP
ADSP ADSC
ADSC
ADSC
ADSC
ADSC ADV
ADV
ADV
ADV
ADV WRITE
WRITE
WRITE
WRITE
WRITE
OE
OE
OE
OE
OE CLK
I/O
Deselected, Power-down
None
X
X
X
X
H
X
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
L
X
X
X
L
L
XXXX
L-H
High-Z
Deselected, Power-down
None
X
L
X
X
L
L
XXXX
L-H
High-Z
Deselected, Power-down
None
X
X
H
X
L
L
XXXX
L-H
High-Z
Deselected, Power-down
None
X
X
X
H
L
L
XXXX
L-H
High-Z
Deselected, Power-down
None
L
X
X
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
L
X
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
H
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
X
H
L
H
L
X
X
X
L-H
High-Z
Read Cycle, Begin Burst
External
H
H
L
L
L
L
X
X
X
L
L-H
Dout
Read Cycle, Begin Burst
External
H
H
L
L
L
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
L
X
L-H
Din
Read Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
H
L
L-H
Dout
Read Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
X
X
H
H
L
H
L
L-H
Dout
Read Cycle, Continue Burst
Next
X
X
X
X
X
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
H
L
L-H
Dout
Read Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
X
X
H
H
L
L
X
L-H
Din
Write Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
L
X
L-H
Din
Read Cycle, Suspend Burst
Current
X
X
X
X
X
HHHH
L
L-H
Dout
Read Cycle, Suspend Burst
Current
X
X
X
X
X
HHHHH
L-H
High-Z
Read Cycle, Suspend Burst
Current
X
X
X
X
H
X
H
H
H
L
L-H
Dout
Read Cycle, Suspend Burst
Current
X
X
X
X
H
X
HHHH
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
X
X
H
H
H
L
X
L-H
Din
Write Cycle, Suspend Burst
Current
X
X
X
X
H
X
H
H
L
X
L-H
Din
Notes:
1. All inputs except
OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care.
WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is LOW.
WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5.
ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and
BWE LOW or GW LOW for the subsequent L-H edge of clock.


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