CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A
FOR
FOR
Document #: 38-08026 Rev. **
Page 10 of 31
troller. The detection of any USB activity, the occurrence of a GPIO Interrupt, or the occurrence of the Cext Interrupt terminates
the suspend condition.
5.3.1
Power-On Reset (POR)
Power-On Reset (POR) occurs every time the power to the device is switched on. Bit 4 of the Status and Control Register is set
to record this event (the register contents are set to 00011001 by the POR). The USB Controller is placed in suspended mode at
the end of POR to conserve power (the clock oscillator, the timers, and the interrupt logic are turned off in suspend mode). After
POR, only a non-idle USB Bus state terminates the suspend mode. The microcontroller then begins execution from ROM address
0x00.
5.3.2
Watch Dog Reset (WDR)
The Watch Dog Timer Reset (WDR) occurs when the Most Significant Bit of the 4-bit Watch Dog Timer Register transitions from
LOW to HIGH. Writing any value to the write-only Watch Dog Restart Register at 0x21 clears the timer (firmware should period-
ically write to the Watch Dog Restart Register in the ‘main loop’ of firmware). The Watch Dog timer is clocked by a 1.024-ms clock
from the free-running timer. If 8 clocks occur between writes to the timer, a WDR occurs and bit 6 of the Status and Control
Register is set to record the event. A Watch Dog Timer Reset lasts for 8.192 ms, at which time the microcontroller begins execution
at ROM address 0x00. The USB transmitter is disabled by a Watch Dog Reset because the USB Device Address Register is
cleared (otherwise, the USB Controller would respond to all address 0 transactions). The transmitter remains disabled until the
WDR bit (bit 6) in the Status and Control Register is reset to 0 by firmware.
Figure 5-4. Watch Dog Reset (WDR)
5.3.3
USB Bus Reset
The USB Controller recognizes a USB Reset when a Single Ended Zero (SE0) condition persists for at least 8–16
µs (the Reset
may be recognized for an SE0 as short as 8
µs, but it is always recognized for an SE0 longer than 16 µs). SE0 is the condition
in which both the D+ line and the D– line are LOW. Bit 5 of the Status and Control Register is set to record this event. If the USB
reset happens while the device is suspended, the suspend condition is cleared and the clock oscillator is restarted. However, the
microcontroller is not released until the USB reset is removed.
5.4
Instant-on Feature (Suspend Mode)
The USB Controller can be placed in a low-power state by setting the Suspend bit (bit 3) of the Status and Control register. All
logic blocks in the device are turned off except the USB receiver, the GPIO interrupt logic, and the Cext interrupt logic. The clock
oscillator and the free-running and watch dog timers are shut down.
The suspend mode is terminated when one of the following three conditions occur:
1. USB activity
2. A GPIO interrupt
3. Cext interrupt
b7
b6
b5
b4
b3
b2
b1
b0
Reserved
WDR
USBR
POR
SUSPEND
Reserved
Reserved
RUN
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
0
0
1
Figure 5-3. Status and Control Register (SCR - Address 0xFF)
Last write to
Watchdog Timer
Register
No write to WDT
register, so WDR
goes HIGH
Execution begins at
Reset Vector 0x00
7.168 to
8.192 ms
8.192 ms
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
