ACS8520 datasheet(77/150 Pages) SEMTECH

Part #	ACS8520

Description	Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems

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Manufacturer	SEMTECH [Semtech Corporation]

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.01/October 2003 © Semtech Corp.

Page 77

www.semtech.com

ACS8520 SETS

Address (hex):

21

Register Name cnfg_ref_source_frequency

_2

Description

(R/W) Configuration of the

frequency and input monitoring

for input I2.

Default Value

0000 0000

Bit 7Bit 6

Bit 5Bit 4

Bit 3Bit 2

Bit 1Bit 0

Set to zero

bucket_id_2

Set to zero

Bit No.

Description

Bit Value

Value Description

[7:6]

Set to zero

00

Set to zero

[5:4]

bucket_id_2

Every input has its own Leaky Bucket used for

activity monitoring. There are four possible

configurations for each Leaky Bucket- see Reg. 50

to Reg. 5F. This 2-bit field selects the configuration

used for input I2.

00

01

10

11

Input I2 activity monitor uses Leaky Bucket

Configuration 0.

Input I2 activity monitor uses Leaky Bucket

Configuration 1.

Input I2 activity monitor uses Leaky Bucket

Configuration 2.

Input I2 activity monitor uses Leaky Bucket

Configuration 3.

[3:0]

Set to zero

0000

8 kHz only

Address (hex):

22

Use <n> = 3

Register Name cnfg_ref_source_frequency

_<n>, where for Reg 22, n =

3

Description

(R/W) Configuration of the

frequency and input monitoring

for input I<n>.

Default Value

0000 0000

Bit 7Bit 6

Bit 5Bit 4

Bit 3Bit 2

Bit 1Bit 0

divn_<n>

lock8k_<n>

bucket_id_<n>

reference_source_frequency_<n>

Bit No.

Description

Bit Value

Value Description

7

divn_<n>

This bit selects whether or not input I<n> is divided

in the programmable pre-divider prior to being input

to the DPLL and frequency monitor- see Reg. 46

and Reg. 47 (cnfg_freq_divn).

0

1

Input I<n> fed directly to DPLL and monitor.

Input I<n> fed to DPLL and monitor via pre-divider.

6

lock8k_<n>

This bit selects whether or not input I<n> is divided

in the preset pre-divider prior to being input to the

DPLL. This results in the DPLL locking to the

reference after it has been divided to 8 kHz. This bit

is ignored when divn_<n> is set (bit =1).

0

1

Input I<n> fed directly to DPLL.

Input I<n> fed to DPLL via preset pre-divider.

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