STK15C68

4-64

SRAM WRITE CYCLES #1 & #2

Note i:

If W is low when E goes low the outputs remain in the high impedance state.

Note j:

E or W must be

≥ V

NO.

SYMBOLS

PARAMETER

STK15C68-25

STK15C68-35

STK15C68-45

UNITS

#1

#2

Alt.

MIN

MAX

MIN

MAX

MIN

MAX

12

Write Cycle Time

25

35

45

ns

13

Write Pulse Width

20

30

35

ns

14

Chip Enable to End of Write

20

30

35

ns

15

Data Set-up to End of Write

10

18

20

ns

16

Data Hold After End of Write

0

0

0

ns

17

Address Set-up to End of Write

20

30

35

ns

18

Address Set-up to Start of Write

0

0

0

ns

19

Address Hold After End of Write

0

0

0

ns

20

h, i

Write Enable to Output Disable

10

17

20

ns

21

Output Active After End of Write

5

5

5

ns

PREVIOUS DATA

DATA OUT

E

ADDRESS

12

W

16

DATA IN

19

13

18

17

DATA VALID

20

15

HIGH IMPEDENCE

21

14

DATA OUT

E

ADDRESS

12

W

16

DATA IN

13

19

18

17

DATA VALID

15

HIGH IMPEDENCE

14