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MCM69F737 Datasheet(PDF) 15 Page - Motorola, Inc |
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MCM69F737 Datasheet(HTML) 15 Page - Motorola, Inc |
15 / 20 page ![]() MCM69F737 15 MOTOROLA FAST SRAM K ADSC ADDRESS WRITE A1 A2 ADSC (INITIATES BURST WRITE) CLOCK STOP (CONTINUE BURST WRITE) WAKE UP ADSC (INITIATES BURST WRITE) D(A1) DATA IN D(A1 + 1) D(A2) DQx HIGH–Z ADV VIH OR VIL FIXED (SEE NOTE) NOTE: While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control lines held in an inactive state. STOP CLOCK WITH WRITE TIMING |
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