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X4045 Datasheet(PDF) 4 Page - Intersil Corporation |
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X4045 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 24 page 4 FN8118.3 December 9, 2015 The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as x 8. The device features an 2-wire interface and software protocol allowing operation on an I2C bus. The device utilizes Intersil’s proprietary Direct Write™ cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION NC VSS VCC SDA SCL 3 2 4 1 6 7 5 8 NC WP RESET 8-Pin JEDEC SOIC, MSOP (PDIP no longer available or supported) Pin (SOIC/MSOP/DIP) Name Function 1 NC No internal connections 2 NC No internal connections 3 RESET/RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below VTRIP. It will remain active until VCC rises above the VTRIP for tPURST. RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. RESET/RESET goes active on power-uppower-up and remains active for 250ms after the power supply stabilizes. RESET is an active high open drain output. An external pull up resistor is required on the RESET/RESET pin. 4VSS Ground 5SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). 6SCL Serial Clock. The Serial Clock input controls the serial bus timing for data input and output. 7WP Write Protect. WP HIGH prevents writes to any location in the device (including the control register). Connect WP pin to VSS when it is not used. 8VCC Supply Voltage X4043, X4045 |
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