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X4043-45 Datasheet(PDF) 17 Page - Intersil Corporation |
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X4043-45 Datasheet(HTML) 17 Page - Intersil Corporation |
17 / 24 page 17 FN8118.3 December 9, 2015 CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V) Notes: (4) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Notes: (5) Typical values are for TA = 25°C and VCC = 5.0V (6) Cb = total capacitance of one bus line in pF. Symbol Parameter Max. Unit Test Conditions COUT(4) Output capacitance (SDA, RESET/RESET) 8 pF VOUT = 0V CIN(4) Input capacitance (SCL, WP) 6 pF VIN = 0V 5V 4.6k RESET 100pF SDA 1533 100pF 5V For VOL= 0.4V and IOL = 3 mA Input pulse levels 0.1 VCC to 0.9 VCC Input rise and fall times 10ns Input and output timing levels 0.5 VCC Output load Standard output load Symbol Parameter 100kHz 400kHz Unit Min. Max. Min. Max. fSCL SCL clock frequency 0 100 0 400 kHz tIN Pulse width suppression time at inputs n/a n/a 50 ns tAA SCL LOW to SDA data out valid 0.1 0.9 0.1 0.9 µs tBUF Time the bus free before start of new transmission 4.7 1.3 µs tLOW Clock LOW time 4.7 1.3 µs tHIGH Clock HIGH time 4.0 0.6 µs tSU:STA Start condition setup time 4.7 0.6 µs tHD:STA Start condition hold time 4.0 0.6 µs tSU:DAT Data in setup time 250 100 ns tHD:DAT Data in hold time 5.0 0 µs tSU:STO Stop condition setup time 0.6 0.6 µs tDH Data output hold time 50 50 ns tR SDA and SCL rise time 1000 20 + .1Cb(6) 300 ns tF SDA and SCL fall time 300 20 + .1Cb(6) 300 ns tSU:WP WP setup time 0.4 0.6 s tHD:WP WP hold time 0 0 s Cb Capacitive load for each bus line 400 400 pF X4043, X4045 |
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