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ISL68201-99125DEMO1Z Datasheet(PDF) 3 Page - Intersil Corporation |
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ISL68201-99125DEMO1Z Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 13 page ISL99125B, ISL99135B 3 FN8848.4 January 24, 2017 Submit Document Feedback Pin Configuration ISL99125B, ISL99135B (24 LD QFN) TOP VIEW 24 23 22 21 20 19 18 17 67 8 9 10 11 12 16 15 14 13 1 2 3 4 5 SW SW SW SW PWM FCCM BOOT GH PHASE VIN PAD2 GND PAD1 Pin Descriptions PIN # PIN NAME DESCRIPTION 1 PWM PWM input of gate driver. The PWM signal can enter three distinct states during operation. Connect this pin to the PWM output of the controller. 2 FCCM Input pin to enable or disable diode emulation. When FCCM is LOW, diode emulation is allowed. When FCCM is HIGH, continuous conduction mode is forced. High impedance on the input (floating FCCM) or keeping the pin at mid-level of VCC will shut down the device into ultra-low current mode (5V, 3μA). 3 BOOT Floating bootstrap supply pin for the upper gate drive. Place a high quality low ESR ceramic capacitor (~0.1μF to 0.22μF/X7R) in close proximity across the BOOT and PHASE pins. 4 GH High-side gate drive output for monitoring/testing. No circuit connection needed. 5 PHASE Return of bootstrap capacitor. Internally connected to SW node. External connection is not needed. 6, 7, 8, 22, PAD2 VIN Input of power stage. Place a couple of high quality, low ESR ceramic capacitors (10μF or higher, X5R or X7R) in close proximity across the VIN and GND planes. 9, 10, 11, 12, 17, 18, 21, PAD1 GND Power stage and logic bias supply return. Connect directly to system ground plane. 13, 14, 15, 16 SW Switching junction node between low-side and high-side MOSFETs. Connect directly to output inductor. 19, 20 GL Low-side gate drive output for monitoring/testing. No circuit connection needed. 23, 24 VCC +5V driver bias supply. Place a high quality, low ESR ceramic capacitor (~1μF/ X5R~X7R) in close proximity from this pin to system ground plane. |
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