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MX7705 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MX7705 Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 34 page ![]() 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC 6 _______________________________________________________________________________________ TIMING CHARACTERISTICS (VDD = 3V or 5V, GND = 0, VREF+ = 1.225V for VDD = 3V and VREF+ = 2.5V for VDD = 5V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.) (Note 16) (Figures 8, 9) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DRDY High Time 500 / fCLKIN s Reset Pulse-Width Low 100 ns DRDY Fall to CS Fall Setup Time t1 0ns CS Fall to SCLK Rise Setup Time t2 120 ns VDD = 4.75V to 5.25V 0 80 SCLK Fall to DOUT Valid Delay t3 VDD = 2.7V to 3.6V 0 100 ns SCLK Pulse-Width High t4 100 ns SCLK Pulse-Width Low t5 100 ns CS Rise to SCLK Rise Hold Time t6 0ns VDD = 4.75V to 5.25V 60 Bus Relinquish Time After SCLK Rising Edge t7 VDD = 2.7V to 3.6V 100 ns SCLK Fall to DRDY Rise Delay t8 100 ns DIN to SCLK Setup Time t9 30 ns DIN to SCLK Hold Time t10 20 ns |
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