 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MX7705 Datasheet(PDF) 26 Page - Maxim Integrated Products |
|
||||||||||||||||||||||||||||||
MX7705 Datasheet(HTML) 26 Page - Maxim Integrated Products |
|
|
26 / 34 page  Reset Drive RESET low to reset the MX7705 to power-on reset status. DRDY goes high and all communication to the MX7705 is ignored while RESET is low. Upon releasing RESET, the device must be reconfigured to begin a con- version. The device returns to waiting for a write to the communication register after a reset has been performed. Perform a calibration sequence following a reset for accurate conversions. The MX7705 clock generator continues to run when RESET is pulled low. This allows any device running from CLKOUT to be uninterrupted when the device is in reset. Selecting Custom Output Data Rates and First-Notch Frequency The recommended frequency range of the external clock is 400kHz to 5MHz. The output data rate and first notch frequency are dependent on the decimation rate of the digital filter. Table 14 shows the available decimation rates of the digital filter. The output data rate and filter first notch is calculated using the following formula: (if CLKDIV = 1) (if CLKDIV = 0) Note: First-notch filter frequency = output data rate. Performing a Conversion At power-on reset, the MX7705 expects a write to the communications register. Writing to the communica- tions register selects the acquisition channel, read/write operation for the next register, power-down/normal mode, and address of the following register to be accessed. The MX7705 has six user-accessible regis- ters, which control the function of the device and allow the result to be read. Write to the communications reg- ister before accessing any other registers. Writing to the clock and setup registers after configuring and initializing the host processor serial port sets up the MX7705. Use self- or system calibrations to minimize off- set and gain errors (see the Calibration section for more details). Set FSYNC = 0 to begin calibration or conver- sion. The MX7705 performs free-running acquisitions when FSYNC is low (see the Using FSYNC section). The µC can poll the DRDY bit of the communications register and read the data register when the DRDY bit returns a 0. For hardware polling, the DRDY output goes low when the new data is valid in the data register. The data register can be read multiple times while the next conversion takes place. The flow diagram in Figure 11 shows an example sequence required to perform a conversion on channel 1 (AIN1+ / AIN1-) after a power-on reset. output data rate f Decimation Rate CLKIN = × 128 output data rate f Decimation Rate CLKIN . = × × 128 05 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC 26 ______________________________________________________________________________________ Table 14. Filter Select and Decimation Rate CLK FS1 FS0 DECIMATION RATE 0 0 0 391 0 0 1 313 01 0 78 01 1 39 1 0 0 384 1 0 1 320 11 0 77 11 1 38 |
Similar Part No. - MX7705 |
|
Similar Description - MX7705 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
