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Si53325-B-GM Datasheet(PDF) 11 Page - Silicon Laboratories |
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Si53325-B-GM Datasheet(HTML) 11 Page - Silicon Laboratories |
11 / 51 page 2.7 Typical Phase Noise Performance: Differential Input Clock Each of the phase noise plots superimposes Source Jitter, Total SE Jitter, and Total Diff Jitter on the same diagram. • Source Jitter—Reference clock phase noise (measured Single-ended to PNA). • Total Jitter (SE)—Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. • Total Jitter (Diff)—Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. For more infor- mation, see 3. Electrical Specifications. Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS). PSPL 5310A CLKx CLKxb 50 50 Balun 50 Ohm AG E5052 Phase Noise Analyzer Si5332x DUT PSPL 5310A CLK SYNTH SMA103A Balun Source jitter measured here Total jitter (Single-Ended) measured here Total jitter (Differential) measured here Figure 2.9. Differential Measurement Method Using a Balun The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calcula- ted (via root-sum-square addition). Frequency (MHz) Differential Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Differential) (fs) Additive Jitter (Differential) (fs) 156.25 1.0 38.2 147.8 142.8 118.3 112.0 Figure 2.10. Total Jitter Differential Input (156.25 MHz) Si53320-28 Data Sheet Functional Description silabs.com | Smart. Connected. Energy-friendly. Rev. 1.2 | 10 |
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