AN131

Rev. 1.3

9

// at 24.5 MHz multiplied by two using the PLL.

//

void SYSCLK_Init (void)

{

int i;

// software timer

char SFRPAGE_SAVE = SFRPAGE;

// Save Current SFR page

SFRPAGE = CONFIG_PAGE;

// set SFR page

OSCICN = 0x83;

// set internal oscillator to run

// at its maximum frequency

CLKSEL = 0x00;

// Select the internal osc. as

// the SYSCLK source

//Turn on the PLL and increase the system clock by a factor of M/N = 2

SFRPAGE = CONFIG_PAGE;

PLL0CN

= 0x00;

// Set internal osc. as PLL source

SFRPAGE = LEGACY_PAGE;

FLSCL

= 0x10;

// Set FLASH read time for 50MHz clk

// or less

SFRPAGE = CONFIG_PAGE;

PLL0CN |= 0x01;

// Enable Power to PLL

PLL0DIV = 0x01;

// Set Pre-divide value to N (N = 1)

PLL0FLT = 0x01;

// Set the PLL filter register for

// a reference clock from 19 - 30 MHz

// and an output clock from 45 - 80 MHz

PLL0MUL = 0x02;

// Multiply SYSCLK by M (M = 2)

for (i=0; i < 256; i++) ;

// Wait at least 5us

PLL0CN

|= 0x02;

// Enable the PLL

while(!(PLL0CN & 0x10));

// Wait until PLL frequency is locked

CLKSEL

= 0x02;

// Select PLL as SYSCLK source

SFRPAGE = SFRPAGE_SAVE;

// Restore SFR page

}

//-----------------------------------------------------------------------------

// PORT_Init

//-----------------------------------------------------------------------------

//

// This routine configures the crossbar and GPIO ports.

//

void PORT_Init (void)

{

char SFRPAGE_SAVE = SFRPAGE;

// Save Current SFR page

SFRPAGE = CONFIG_PAGE;

// set SFR page

XBR0

= 0x00;

XBR1

= 0x00;