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CY7C64601 Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C64601
Description  EZ-USB FX USB Microcontroller Data Sheet
Download  42 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C64601 Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY7C64601/603/613
Document #: 38-08005 Rev. **
Page 7 of 42
Endpoint data is serviced either directly by the 8051, or moved on or off-chip using the DMA system built into the CY7C646xx.
Bulk data is available in 64-byte random-access buffers that can also be addressed as a FIFO using the special AutoPointer
feature. Each endpoint has a unique interrupt vector. This allows ISRs (Interrupt Service Routines) automatically to be called with
minimum overhead and latency, simply by including the ISR address in an interrupt jump table.
2.4
Default USB Machine
When the CY7C64613 is plugged into USB with no EEPROM attached to its I2C port (but with the SCL and SDA pull-ups
installed), the intelligent SIE enumerates as a generic USB device with the following characteristics:
Powering up with default USB characteristics allows code to be written without initial consideration of the enumeration code that
establishes the default USB device, speeding the learning process.
2.5
IBN (In-Bulk-NAK) Interrupts
The CY7C646xx has an interrupt that indicates that an IN token has been received by an endpoint, and the SIE has NAK’d the
transfer due to no data being available in the endpoint buffer. Interrupt request bits are provided for endpoints EP1N through
EP7IN, and a previously reserved vector is added to the USB vectored interrupts.
2.6
Slave FIFOs
Many high-bandwidth USB designs use a FIFO between the USB interface chip and external logic to match data rates, or to
smooth the USB data delivery (which, being packet oriented, occurs in bursts). The CY7C646xx moves this glue logic into the
part by providing four 64-byte internal slave FIFOs. The FIFOs also provide two important interface functions, external clocking
and bus width conversion.
Using external clocking, external logic (such as a DSP or ASIC) can clock data into or out of the slave FIFOs under control of its
own clock, rather than synchronizing with the clock supplied by the CY7C646xx (24 or 48 MHz). The FIFOs can be controlled
ID bytes (hex)
VID (Vendor ID)
0547
PID (Product ID)
2235
DID (Device ID)
0000
Default Endpoints
Endpoint
Type
Alternate Setting
0
1
2
Max Packet Size (bytes)
0
CTL
64
64
64
1 IN
INT
0
16
64
2 IN
BULK
0
64
64
2 OUT
BULK
0
64
64
4 IN
BULK
0
64
64
4 OUT
BULK
0
64
64
6 IN
BULK
0
64
64
6 OUT
BULK
0
64
64
8 IN
ISO
0
16
256
8 OUT
ISO
0
16
256
9 IN
ISO
0
16
16
9 OUT
ISO
0
16
16
10 IN
ISO
0
16
16
10 OUT
ISO
0
16
16


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