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709269S12PFG Datasheet(PDF) 1 Page - Integrated Device Technology |
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709269S12PFG Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 17 page ©2015 Integrated Device Technology, Inc. JUNE 2015 DSC-3243/15 1 Functional Block Diagram Features ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed clock to data access – Commercial:9/12/15ns(max.) – Industrial: 12ns (max.) ◆ Low-power operation – IDT709279/69S Active: 950mW (typ.) Standby: 5mW (typ.) – IDT709279/69L Active: 950mW (typ.) Standby: 1mW (typ.) ◆ Flow-Through or Pipelined output mode on either port via the FT/PIPE pin ◆ Dual chip enables allow for depth expansion without additional logic ◆ Counter enable and reset features ◆ Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all control, data, and addressinputs – Data input, address, and control registers – Fast 9ns clock to data out in the Pipelined output mode – Self-timedwriteallowsfastcycletime – 15ns cycle time, 67MHz operation in Pipelined output mode ◆ Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility ◆ TTL- compatible, single 5V (±10%) power supply ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Available in a 100-pin Thin Quad Flatpack (TQFP) package ◆ Green parts available. See ordering information HIGH-SPEED 32/16K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM IDT709279/69S/L FT/PIPER R/ WR UBR LBR CE0R OER CE1R I/O Control MEMORY ARRAY Counter/ Address Reg. I/O Control 3243 drw 01 A14R(1) A0R CLKR ADSR CNTENR CNTRSTR I/O8L- I/O15L I/O0L-I/O7L I/O8R-I/O15R I/O0R-I/O7R A0L CLKL ADSL A14L(1) CNTENL CNTRSTL Counter/ Address Reg. R/ WL UBL LBL CE0L OEL CE1L , 0a 1a 0b 1b 0/1 ab 1 0/1 0 FT/PIPEL , 1 0/1 0 1a 0a 1b 0b 0/1 ba NOTE: 1. A14X is a NC for IDT709269. |
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