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IDT71V3558XSA133BGG Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT71V3558XSA133BGG Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 25 page  6.42 8 IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT ™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Pin Configuration - 128K x 36, 165 fBGA Pin Configuration - 256K x 18, 165 fBGA 1 2 3 4567 89 10 11 ANC(2) A7 CE1 BW3 BW2 CE2 CEN ADV/LD NC(2) A8 NC BNC A6 CE2 BW4 BW1 CLK R/W OE NC(2) A9 NC(2) CI/OP3 NC VDDQ VSS VSS VSS VSS VSS VDDQ NC I/OP2 DI/O17 I/O16 VDDQ VDD VSS VSS VSS VDD VDDQ I/O15 I/O14 EI/O19 I/O18 VDDQ VDD VSS VSS VSS VDD VDDQ I/O13 I/O12 FI/O21 I/O20 VDDQ VDD VSS VSS VSS VDD VDDQ I/O11 I/O10 GI/O23 I/O22 VDDQ VDD VSS VSS VSS VDD VDDQ I/O9 I/O8 HVDD(1) VDD(1) NC VDD VSS VSS VSS VDD NC NC NC/ZZ(5) JI/O25 I/O24 VDDQ VDD VSS VSS VSS VDD VDDQ I/O7 I/O6 KI/O27 I/O26 VDDQ VDD VSS VSS VSS VDD VDDQ I/O5 I/O4 LI/O29 I/O28 VDDQ VDD VSS VSS VSS VDD VDDQ I/O3 I/O2 MI/O31 I/O30 VDDQ VDD VSS VSS VSS VDD VDDQ I/O1 I/O0 NI/OP4 NC VDDQ VSS NC/TRST(3,4) NC VDD(1) VSS VDDQ NC I/OP1 PNC NC(2) A5 A2 NC/TDI(3) A1 NC/TDO(3) A10 A13 A14 NC R LBO NC(2) A4 A3 NC/TMS(3) A0 NC/TCK(3) A11 A12 A15 A16 5281 tbl 25 1 23456 7 8 9 10 11 ANC(2) A7 CE1 BW2 NC CE2 CEN ADV/LD NC(2) A8 A10 BNC A6 CE2 NC BW1 CLK R/W OE NC(2) A9 NC(2) CNC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC I/OP1 DNC I/O8 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O7 ENC I/O9 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O6 FNC I/O10 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O5 GNC I/O11 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O4 HVDD(1) VDD(1) NC VDD VSS VSS VSS VDD NC NC NC/ZZ(5) JI/O12 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O3 NC KI/O13 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O2 NC LI/O14 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O1 NC MI/O15 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O0 NC NI/OP2 NC VDDQ VSS NC/TRST(3,4) NC VDD(1) VSS VDDQ NC NC PNC NC(2) A5 A2 NC/TDI(3) A1 NC/TDO(3) A11 A14 A15 NC R LBO NC(2) A4 A3 NC/TMS(3) A0 NC/TCK(3) A12 A13 A16 A17 5281 tbl 25a NOTES: 1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH. 2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively. 3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. 4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD. 5. Pin H11 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode). |
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