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709279S9PFGI Datasheet(PDF) 8 Page - Integrated Device Technology |
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709279S9PFGI Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 17 page 6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 8 Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(3,7) Timing Waveform of Read Cycle for Pipelined Output (FT/PIPE"X" = VIH)(3,7) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 7. "x" denotes Left or Right port. The diagram is with respect to that port. An An + 1 An + 2 An + 3 tCYC1 tCH1 tCL1 R/ W ADDRESS DATAOUT CE0 CLK OE tSC tHC tCD1 tCKLZ Qn Qn +1 Qn +2 tOHZ tOLZ tOE tCKHZ 3243 drw 07 (1) (1) (1) (1) (2) CE1 UB, LB (4) tSB tHB tSW tHW tSA tHA tDC tDC (5) tSC tHC tSB tHB An An + 1 An + 2 An + 3 tCYC2 tCH2 tCL2 R/ W ADDRESS CE0 CLK CE1 UB, LB (4) DATAOUT OE tCD2 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE 3243 drw 08 (1) (1) (1) (2) tSC tHC tSB tHB tSW tHW tSA tHA tDC tSC tHC tSB tHB (5) (1 Latency) (6) (6) |
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