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709379L12PFG8 Datasheet(PDF) 4 Page - Integrated Device Technology |
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709379L12PFG8 Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 16 page 6.42 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 4 Recommended Operating Temperature and Supply Voltage Recommended DC Operating Conditions NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%. 3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected. Absolute Maximum Ratings(1) NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. Capacitance(1) (TA = +25°C, f = 1.0MHz) NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. NOTES: 1. VTERM must not exceed VCC + 10%. 2. VIL > -1.5V for pulse width less than 10ns. Grade Ambient Temperature(2) GND VCC Commercial 0OC to +70OC0V 5.0V + 10% Industrial -40OC to +85OC0V 5.0V + 10% 4845 tbl 04 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 ____ 6.0(1) V VIL Input Low Voltage -0.5(2) ____ 0.8 V 4845 tbl 05 Symbol Parameter Conditions(2) Max. Unit CIN Input Capacitance VIN = 3dV 9 pF COUT(3) Output Capacitance VOUT = 3dV 10 pF 4845 tbl 07 Symbol Rating Commercial & Industrial Unit VTERM(2) Terminal Voltage with Respect to GND -0.5 to +7.0 V TBIAS Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -65 to +150 o C TJN Junction Temperature +150 o C IOUT DC Output Current 50 mA 4845 tbl 06 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB. 6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily. Truth Table II—Address Counter Control(1,2,6) External Address Previous Internal Address Internal Address Used CLK ADS CNTEN CNTRST I/O(3) MODE An X An ↑ L(4) XH DI/O (n) External Address Used XAn An + 1 ↑ H L(5) HDI/O(n+1) Counter Enabled—Internal Address generation X An + 1 An + 1 ↑ HH H DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused) XX A0 ↑ XX L(4) DI/O(0) Counter Reset to Address 0 4845 tbl 03 |
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