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IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with

2.5V I/O, Burst Counter and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol

Pin Function

I/O

Active

Description

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combination of the rising edge of

CLK, ADV/

ADV/

LD

Advance / Load

I

N/A

ADV/

when it is sampled low at the rising edge of clock with the chip selected. When ADV/

chip deselected, any burst in progress is terminated. When ADV/

burst counter is advanced for any burst that was in progress. The external addresses are ignored when

ADV/

R/

W

Read / Write

I

N/A

R/

Write access to the memory array. The data bus activity for the current cycle takes place one clock

cycle later.

CEN

Clock Enable

I

LOW Synchronous Clock Enable Input. When

clock are ignored and outputs remain unchanged. The effect of

outputs is as if the low to high clock transition did not occur. For normal operation,

sampled low at rising edge of clock.

Individual Byte

Write Enables

I

LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write

cycles (When R/

valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are

ignored when R/

later.

Chip Enables

I

LOW Synchronous active low chip enable.

(

deselect is initiated.

Chip Enable

I

inverted polarity but otherwise identical to

CLK

Clock

I

N/A

This is the clock input to the IDT71T75702/902. Except for

made with respect to the rising edge of CLK.

Data Input/Output

I/O

N/A

Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The

data output path is flow-through (no output register).

LBO

Linear Burst Order

I

LOW Burst ord er selection input. When

low the Linear burst sequence is selected.

operation.

OE

Output Enable

I

LOW

Asynchronous output enable.

the I/O pins are in a high-impedance state.

write cycles. In normal operation,

TMS

Test Mode Select

I

N/A

Gives input command for TAP controller; sampled on rising edge of TCK. This pin has an internal pullup.

TDI

Test Data Input

I

N/A

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an

internal pullup.

TCK

Test Clock

I

N/A

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of

TCK, while test outputs are driven from falling edge of TCK. This pin has an internal pullup.

TDO

Test Data Output

O

N/A

Serial output of registers placed between TDI and TDO. This output is active d epending on the state of

the TAP controller.

TRST

JTAG Reset

(Optional)

ILOW

Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG

reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not

used

ZZ

Sleep Mode

I

HIGH

Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71T75702/902 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.

This pin has an internal pulldown.

Power Supply

N/A

N/A

2.5V core power supply.

Power Supply

N/A

N/A

2.5V I/O Supply.

Ground

N/A

N/A

Ground.

5319 tbl 02