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ICX408AK Datasheet(PDF) 7 Page - Sony Corporation |
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ICX408AK Datasheet(HTML) 7 Page - Sony Corporation |
7 / 18 page – 7 – ICX408AK Clock Switching Characteristics Item Readout clock Vertical transfer clock Reset gate clock Substrate clock VT V φ1, Vφ2, V φ3, Vφ4 H φ1 H φ2 H φ1 H φ2 φRG φSUB 2.3 26 26 11 1.5 2.5 28.5 28.5 5.38 13 1.8 26 26 28.5 28.5 5.38 51 0.5 6.5 6.5 0.01 0.01 3 9.5 9.5 0.5 15 0.5 6.5 6.5 0.01 0.01 3 250 9.5 9.5 0.5 µs ns ns µs ns µs During readout ∗1 ∗2 During drain charge Symbol twh Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. twl tr tf Unit Remarks ∗1 When vertical transfer clock driver CXD1267AN is used. ∗2 tf ≥ tr – 2ns, and the cross-point voltage (V CR ) for the H φ1 rising side of the Hφ1 and Hφ2 waveforms must be at least V φH/2 [V]. During imaging During parallel-serial conversion Item Horizontal transfer clock H φ1, Hφ2 22 26 ns ∗3 Symbol two Min. Typ. Max. Unit Remarks ∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ 1 and H φ2 is two. |
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