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HY62KF08802B-DD Datasheet(PDF) 7 Page - Hynix Semiconductor |
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HY62KF08802B-DD Datasheet(HTML) 7 Page - Hynix Semiconductor |
7 / 10 page HY62KF08802B Series Rev.00 / Jan.02 6 WRITE CYCLE 1 (1,4,8) (/WE Controlled) WRITE CYCLE 2 (Note 1,4,8) (/CS1, CS2 Controlled) Notes: 1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2. 2. tWR is measured from the earlier of /CS1or /WE going high or CS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS1, CS2 high transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. Transition is measured + 200mV from steady state. This parameter is sampled and not 100% tested. 8. /CS1 in high for the standby, low for active. CS2 in low for the standby, high for active. Data Valid ADDR Data Out /CS1 CS2 /WE tWC tCW tWR(2) tAW tWP Data In High-Z tAS tWHZ(3,7) tDW tDH tOW (5) (6) Data Valid ADDR Data Out /CS1 CS2 /WE tWC tCW tWR(2) tAW tWP Data In tDW tDH High-Z High-Z tAS |
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