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ICX405AK Datasheet(PDF) 2 Page - Sony Corporation |
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ICX405AK Datasheet(HTML) 2 Page - Sony Corporation |
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2 / 18 page  – 2 – ICX405AK Block Diagram and Pin Configuration (Top View) 6 7 Note) Horizontal Register 2 3 4 Cy Cy G G Cy Mg Ye Ye Mg Mg Ye G Cy Cy G G Cy Mg Ye Ye Mg Mg Ye G 8 1 10 11 12 14 9 16 13 15 5 Note) : Photo sensor Pin No. 1 2 3 4 5 6 7 8 V φ4 V φ3 V φ2 V φ1 GND NC NC VOUT Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Signal output 9 10 11 12 13 14 15 16 VDD GND φSUB VL φRG NC H φ1 H φ2 Supply voltage GND Substrate clock Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock Symbol Description Pin No. Description Pin Description Symbol Absolute Maximum Ratings ∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. Against φSUB Against GND Against VL Between input clock pins Storage temperature Operating temperature –40 to +8 –50 to +15 –50 to +0.3 –40 to +0.3 –0.3 to +20 –10 to +18 –10 to +6 –0.3 to +28 –0.3 to +15 to +15 –6 to +6 –14 to +14 –30 to +80 –10 to +60 V V V V V V V V V V V V °C °C VDD, VOUT, φRG – φSUB V φ1, Vφ3 – φSUB V φ2, Vφ4, VL – φSUB H φ1, Hφ2, GND – φSUB VDD, VOUT, φRG – GND V φ1, Vφ2, Vφ3, Vφ4 – GND H φ1, Hφ2 – GND V φ1, Vφ3 – VL V φ2, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins H φ1 – Hφ2 H φ1, Hφ2 – Vφ4 Item Ratings Unit Remarks ∗1 |
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