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HY62KF08802B Datasheet(PDF) 2 Page - Hynix Semiconductor |
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HY62KF08802B Datasheet(HTML) 2 Page - Hynix Semiconductor |
2 / 10 page HY62KF08802B Series Rev.00 / Jan.02 2 DESCRIPTION The HY62KF08802B is a high speed, super low power and 8Mbit full CMOS SRAM organized as 1M words by 8bits. The HY62KF08802B uses high performance full CMOS process technology and is designed for high speed and low power circuit technology. It is particularly well-suited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. FEATURES • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup -. 1.2V(min) data retention • Standard pin configuration -. 44pin 400mil TSOP-II (Forward) Standby Current(uA) Product No. Voltage (V) Speed (ns) Operation Current/Icc(mA) SL LL Temperature ( °C) HY62KF08802B-I 2.7~3.6 55/70 2 12 30 -40~85 Note 1. I : Industrial 2. Current value is max. PIN CONNECTION BLOCK DIAGRAM PIN DESCRIPTION Pin Name Pin Function Pin Name Pin Function /CS1, CS2 Chip Select A0~A19 Address Inputs /WE Write Enable Vcc Power (2.7~3.6V) /OE Output Enable Vss Ground I/O1~I/O8 Data Inputs/Outputs NC No Connection A5 A6 /OE CS2 A8 NC NC I/O8 I/O7 Vss Vcc I/O6 I/O5 NC NC A9 A10 A11 A12 A13 A14 A7 A4 A3 A2 A1 A0 /CS1 NC NC I/O1 I/O2 Vcc Vss I/O3 I/O4 NC NC /WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 TSOPII (Forward) MEMORY ARRAY 1M x 8 ROW DECODER I/O1 I/O8 A0 A19 /CS1 CS2 /OE /WE |
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