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S-8249AAY-M6T1U Datasheet(PDF) 11 Page - Seiko Instruments Inc |
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S-8249AAY-M6T1U Datasheet(HTML) 11 Page - Seiko Instruments Inc |
11 / 22 page VOLTAGE MONITORING IC WITH CELL BALANCING FUNCTION Rev.1.2_00 S-8249 Series 11 Operation Remark Refer to " Standard Circuit". 1. Normal status In the S-8249 Series, if the voltage between the VDD pin and the VSS pin (VDS) has not reached the cell balancing detection voltage (VBU), the CB pin output is in the high-impedance status. The CO pin output status varies according to the output form and output logic selected, as shown in Table 10. This is the normal status. Table 10 CO Pin Output Form and Output Logic CB Pin Output CO Pin Output CMOS output, active "H" "H" "L" CMOS output, active "L" "H" "H" Nch open-drain output, active "H" "H" "L" Nch open-drain output, active "L" "H" "H" 2. Cell balancing status In the S-8249 Series, if VDS is VBU or higher and this status continues for the cell balancing detection delay time (tBU) or longer, the CB pin output becomes "L". This is the cell balancing status. The cell balancing status is released when VDS drops to the cell balancing release voltage (VBL) or lower and this status continues for the cell balancing release delay time (tBL) or longer. The S-8249 Series includes an Nch transistor with ON resistance of 5 Ω typ. (RCBON) between the CB pin and the VSS pin, thus causing the cell balancing current (ICB) to flow in cell balancing status, and the cell balancing operation to start. By connecting a resistor (RCB) to the CB pin, ICB in cell balancing status can be calculated by using the following equation. ICB = VBU / (RCBON + RCB) CB RCB VSS VDD S-8249 Series ICB RCBON = 5 Ω typ. Control circuit Figure 5 |
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