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TCS34723 Datasheet(PDF) 23 Page - ams AG |
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TCS34723 Datasheet(HTML) 23 Page - ams AG |
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23 / 40 page  ams Datasheet Page 23 [v1-02] 2016-Feb-08 Document Feedback TCS3472 − Register Description RGBC Timing Register (0x01) The RGBC timing register controls the internal integration time of the RGBC clear and IR channel ADCs in 2.4-ms increments. Max RGBC Count = (256 − ATIME) × 1024 up to a maximum of 65535. Figure 27: RGBC Timing Register Wait Time Register (0x03) Wait time is set 2.4 ms increments unless the WLONG bit is asserted, in which case the wait times are 12× longer. WTIME is programmed as a 2’s complement number. Figure 28: Wait Time Register Fields Bits Description ATIME 7:0 VALUE INTEG_CYCLES TIME MAX COUNT 0xFF 1 2.4 ms 1024 0xF6 10 24 ms 10240 0xD5 42 101 ms 43008 0xC0 64 154 ms 65535 0x00 256 700 ms 65535 Fields Bits Description WTIME 7:0 REGISTER VALUE WAIT TIME TIME (WLONG= 0) TIME (WLONG= 1) 0xFF 1 2.4 ms 0.029 sec 0xAB 85 204 ms 2.45 sec 0x00 256 614 ms 7.4 sec |
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