FDC37B774 datasheet(12/196 Pages) SMSC

Part #	FDC37B774

Description	ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES

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Manufacturer	SMSC [SMSC Corporation]

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FUNCTIONAL DESCRIPTION

SUPER I/O REGISTERS

The address map, shown below in Table 1,

shows the addresses of the different blocks of

the Super I/O immediately after power up. The

base addresses of the FDC, serial and parallel

ports can be moved via the configuration

registers. Some addresses are used to access

more than one register.

HOST PROCESSOR INTERFACE

The host processor communicates with the

FDC37B77x through a series of read/write

registers. The port addresses for these registers

are shown in Table 1.

Register access is

accomplished through programmed I/O or DMA

transfers. All registers are 8 bits wide. All host

interface output buffers are capable of sinking a

minimum of 12 mA.

Table 1 - Super I/O Block Addresses

ADDRESS

BLOCK NAME

LOGICAL

DEVICE

NOTES

Base+(0-5) and +(7)

Floppy Disk

0

Base+(0-7)

Serial Port Com 1

4

Base1+(0-7)

Base2+(0-7)

Serial Port Com 2

5

IR Support

Fast IR

Base+(0-3)

Base+(0-7)

Base+(0-3), +(400-402)

Base+(0-7), +(400-402)

Parallel Port

SPP

EPP

ECP

ECP+EPP+SPP

3

60, 64

KYBD

7

Note 1: Refer to the configuration register descriptions for setting the base address

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