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UPSD323X Datasheet(PDF) 79 Page - STMicroelectronics |
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UPSD323X Datasheet(HTML) 79 Page - STMicroelectronics |
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79 / 176 page  79/176 µPSD323X Serial Status Register (SxSTA: S1STA, S2STA) SxSTA is a “Read-only” register. The contents of this register may be used as a vector to a service routine. This optimized the response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the I2C- bus interface are given Table 54. This flag is set, and an interrupt is generated, after any of the following events occur. 1. Own slave address has been received during AA = 1: ack_int 2. The general call address has been received while GC(SxADR.0) = 1 and AA = 1: 3. A data byte has been received or transmitted in Master Mode (even if arbitration is lost): ack_int 4. A data byte has been received or transmitted as selected slave: ack_int 5. A stop condition is received as selected slave receiver or transmitter: stop_int Data Shift Register (SxDAT: S1DAT, S2DAT) SxDAT contains the serial data to be transmitted or data which has just been received. The MSB (Bit 7) is transmitted or received first; that is, data shifted from right to left. Table 53. Serial Status Register (SxSTA) Table 54. Description of the SxSTA Bits Note: 1. Interrupt Flag Bit (INTR, SxSTA Bit 5) is cleared by Hardware as reading SxSTA register. 2. I2C interrupt flag (INTR) can occur in below case. (except DDC2B Mode at SWENB= 0) Table 55. Data Shift Register (SxDAT: S1DAT, S2DAT) 76543210 GC STOP INTR TX_MODE BBUSY BLOST /ACK_REP SLV Bit Symbol Function 7 GC General Call Flag 6 STOP Stop Flag. This bit is set when a STOP condition is received 5 INTR Interrupt Flag. This bit is set when an I C Interrupt condition is requested 4 TX_MODE Transmission Mode Flag. This bit is set when the I C is a transmitter; otherwise this bit is reset 3 BBUSY Bus Busy Flag. This bit is set when the bus is being used by another master; otherwise, this bit is reset 2 BLOST Bus Lost Flag. This bit is set when the master loses the bus contention; otherwise this bit is reset 1 /ACK_REP Acknowledge Response Flag. This bit is set when the receiver transmits the not acknowledge signal This bit is reset when the receiver transmits the acknowledge signal 0SLV Slave Mode Flag. This bit is set when the I C plays role in the Slave Mode; otherwise this bit is reset 76543210 SxDAT7 SxDAT6 SxDAT5 SxDAT4 SxDAT3 SxDAT2 SxDAT1 SxDAT0 |
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