LVDS Interface

DCLKIN(A,B,C,D),DVALID(A,B,C,D),DIN(A,B,C,D)[15:])

DLPC910

DLP9000XFLS

APPS

FPGA

DOUT(A,B,C,D)[15:0]

DCLKOUT (A,B,C,D)

SCTRL(A,B,C,D)

RESET_ADDR(3:0)

RESET_MODE(1:0)

RESET_SEL(1:0)

RESET_STRB

RESET_OEZ

RESET_IRQZ

SCP BUS(3:0)

Power Management

OSC

50 MHz

CTRL_RSTZ

JTAG(3:0)

DLPR910

PGM(4:0)

USER

Interface

Connectivity

USB

Ethernet

Volatile

And

Non-volatile

Storage

I2C

Row and Block Signals

ROWMD(1:0),ROWAD(10:0),BLKMD(1:0),BLKAD(3:0),RST2BLKZ

Control Signals

COMP_DATA,NS_FLIP,WDT_ENBLZ,PWR_FLOAT

Status Signals

RST_ACTIVE,INIT_ACTIVE,ECP2_FINISHED

RESETZ

VLED0

VLED1

Illumination

Driver

Illumination

Sensor

10

DLPR910

DLPS065B – SEPTEMBER 2015 – REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: DLPR910

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Copyright © 2015–2016, Texas Instruments Incorporated

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DLPR910 configuration PROM comes pre-programmed with configuration code for the DLPC910. Upon

power-up, the DLPC910 and the DLPR910 handshake with each other to enable configuration information to be

sent from the DLPR910 to the DLPC910, such that the DLPC910 can configure itself for proper operation within

the application. Without the DLPR910 properly connected to the DLPC910 in the application system, the

DLPC910 would not be able to boot itself and the system would remain inoperable.

8.2 Typical Application

A typical use case for a high speed lithography application is shown in Figure 3 and in Figure 4. Both

applications offer continuous run of printing by changing the digitally created patterns without stopping the

imaging head. The DLPR910 prom configures the DLPC910 digital controller to reliably operate with the

DLP9000X DMD or the DLP6500 DMDs. These chipset combinations provide an ideal back-end imager that

takes in digital images at 2560 × 1600 and 1920 x 1080 in resolution to achieve speeds greater than 61 Gigabits

per second (Gbps) and 24 Gbps respectively. For complete details of this typical application refer to the

DLPC910 data sheet listed in Related Documentation.

Figure 3. Typical High Speed DLP9000X Application Schematic