11

DLP660TE

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DLPS072 – JANUARY 2017

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(1)

(2)

(3)

(4)

(5)

(6)

LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(7)

The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the

window edge as defined in Figure 11. The locations of thermal test points TP2, TP3, TP4 and TP5 in Figure 11 are intended to measure

the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature,

that point should be used.

(8)

Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in

Figure 11. The window test points TP2, TP3, TP4 and TP5 shown in Figure 11 are intended to result in the worst case delta. If a

particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

Supply Voltages

– 0.5

2.3

V

– 0.5

2.3

V

– 0.5

11

V

– 0.5

19

V

– 15

-0.3

V

0.3

V

11

V

34

V

Input Voltages

– 0.5

V

– 0.5

V

500

mV

6.25

mA

Clocks

Clock frequency for LVDS interface, DCLK_A

400

MHz

Clock frequency for LVDS interface, DCLK_B

400

MHz

Clock frequency for LVDS interface, DCLK_C

400

MHz

Clock frequency for LVDS interface, DCLK_D

400

MHz

Environmental

0

90

°C

Temperature,

– 40

90

°C

Absolute Temperature delta between any point on the

30

°C

Dew Point Temperature, operating and non–operating

(noncondensing)

81

°C