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NECVR4102 Datasheet(PDF) 29 Page - Epson Company |
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NECVR4102 Datasheet(HTML) 29 Page - Epson Company |
29 / 420 page Epson Research and Development Page 21 Vancouver Design Center Hardware Functional Specification SED1374 Issue Date: 99/04/29 X26A-A-001-02 5.2.3 Clock Input 5.2.4 Miscellaneous 5.2.5 Power Supply FPLINE O 38 CN3 0 Line Pulse FPSHIFT O 28 CN3 0 Shift Clock LCDPWR O 43 CO1 0 if CNF4 = 1 1 if CNF4 = 0 LCD Power Control DRDY O 42 CN3 0 This pin has multiple functions. • TFT/MD-TFD Display Enable (DRDY). • LCD Backplane Bias (MOD). • Second Shift Clock (FPSHIFT2). See “LCD Interface Pin Mapping” for summary. Pin Name Type Pin # Driver Description CLKI I 51 C Input Clock Pin Name Type Pin # Cell RESET# State Description CNF[4:0] I 45, 46, 47, 48, 49 C As set by hardware These inputs are used to configure the SED1374 - see “Summary of Configuration Options”. Must be connected directly to IO VDD or VSS. GPIO0 I/O, I 22 CS/ TS1 Input This pin has multiple functions - see REG[03h] bit 2. • General Purpose Input/Output pin. • Hardware Power Save. TESTEN I 44 CD High Impedance Test Enable input. This input must be connected to VSS. Pin Name Type Pin # Driver Description COREVDD P 1, 21, 41, 61 PCore VDD IOVDD P 10, 29, 52 P IO VDD VSS P 20, 27, 40, 50, 60, 72, 80 P Common VSS Pin Name Type Pin # Cell RESET# State Description |
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