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709089S9PFG8 Datasheet(PDF) 3 Page - Integrated Device Technology |
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709089S9PFG8 Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 17 page 6.42 IDT709089/79S/L High-Speed 64/32K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 3 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0 and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0 and CE1. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1. Truth Table II—Address Counter Control(1,2) Truth Table I— Read/Write and Enable Control(1,2,3) NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. OE CLK CE0 CE1 R/W I/O0-7 Mode X ↑ H X X High-Z Deselected X ↑ X L X High-Z Deselected X ↑ LH L DIN Write L ↑ LH H DOUT Read H X L H X High-Z Outputs Disabled 3242 tbl 02 External Address Previous Internal Address Internal Address Used CLK ADS CNTEN CNTRST I/O(3) MODE An X An ↑ L(4) XH DI/O (n) External Address Used XAn An + 1 ↑ H L(5) HDI/O(n+1) Counter Enabled—Internal Address generation X An + 1 An + 1 ↑ HH H DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused) XX A0 ↑ XX L(4) DI/O(0) Counter Reset to Address 0 5640 tbl 03 Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A15L(1) A0R - A15R(1) Address I/O0L - I/O7L I/O0R - I/O7R Data Input/Output CLKL CLKR Clock ADSL ADSR Address Strobe CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through/Pipeline VCC Power GND Ground 3242 tbl 01 NOTE: 1. A15X is a NC for IDT709079. |
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