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70914S20PFG8 Datasheet(PDF) 8 Page - Integrated Device Technology |
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70914S20PFG8 Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 12 page 6.42 8 IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Commercial Temperature Range Timing Waveform of Read Cycle, Either Side NOTES: 1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. CEL = CER = VIL, CLKENL = CLKENR = VIL. 3. OE = VIL for the reading port, port 'B'. 4. All timing is the same for left and right ports. Ports "A" may be either the left or right port. Port "B" is opposite from port "A". 5. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD. tCWDD does not apply in this case. Timing Waveform of Write with Port-to-Port Read(2,3,4) DATA IN "A" CLK "B" R/ W "B" ADDR "A" R/ W "A" CLK "A" ADDR "B" NO MATCH MATCH NO MATCH MATCH VALID tCWDD tCD tDC DATA OUT "B" 3490 drw 09 VALID VALID tCCS (5) tCD An An + 1 An + 2 An + 3 tCYC tCH tCL tSCK tHCK tSCK R/ W ADDRESS DATAOUT CE CLKEN CLK OE tS tH tCD tDC tCKLZ Qn Qn + 1 Qn + 1 tOHZ tOLZ tOE tCKHZ 3490 drw 08 (1) (1) (1) (1) |
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