IDT709149S datasheet(4/10 Pages) IDT

Part #	IDT709149S

Description	HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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4 / 10 page

6.42

IDT709149S

High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

4

1

2

3

4

5

6

7

8

20 40

100

60 80

120 140 160 180 200

∆tCD

(Typical, ns)

Capacitance (pF)

3494 drw 05

-1

0

9pF is the I/O capacitance

of this device, and 30pF is the

AC Test Load Capacitance

,

Figure 3. Typical Output Derating (Lumped Capacitive Load).

Figure 1. AC Output Test load.

Figure 2. Output Test Load

(For tCKLZ, tCKHZ, tOLZ, and tOHZ).

*Including scope and jig.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(4) (VCC = 5V ± 10%)

AC Test Conditions

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCLK, using "AC TEST CONDITIONS" at input levels of

GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC = 150mA (Typ).

709149S8

Com'l Only

709149S10

Com'l

& Ind

709149S12

Com'l Only

Symbol

Parameter

Test Condition

Version

Typ.

Max.

Typ.

Max.

Typ.

Max.

Unit

ICC

Dynamic Operating

Current

(Both Ports Active)

CEL

and CER = VIL,

Outputs Disabled

f = fMAX(1)

COM'L

200

320

190

310

180

300

mA

IND

____

190

340

____

ISB1

Standby Current

(Both Ports - TTL

Level Inputs)

CEL

and CER = VIH

f = fMAX(1)

COM'L

100

150

90

150

85

140

mA

IND

____

90

175

____

ISB2

Standby Current

(One Port - TTL

Level Inputs)

CE"A"

= VIL and CE"B" = VIH(3)

Active Port Outputs Disabled,

f=fMAX(1)

COM'L

180

230

170

220

160

210

mA

IND

____

170

250

____

ISB3

Full Standby Current

(Both Ports - All

CMOS Level Inputs)

CEL

and

CER

> VCC - 0.2V,

VIN > VCC - 0.2V or

VIN < 0.2V, f = 0(2)

COM'L

5

15

5

15

5

15

mA

IND

____

520

____

ISB4

Full Standby Current

(One Port - All

CMOS Level Inputs)

CE"A"

< 0.2V and

CE"B"

> VCC - 0.2V(3)

VIN > VCC - 0.2V or VIN < 0.2V

Active Port Outputs Disabled,

f = fMAX(1)

COM'L

170

220

160

210

150

200

mA

IND

____

160

240

____

3494 tbl 06

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns Max.

1.5V

Figures 1,2 and 3

3494 tbl 07

3494 drw 04

893

Ω

30pF

347

Ω

5V

DATAOUT

893

Ω

5pF*

347

Ω

5V

DATAOUT

3494 drw 03

,

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