6.42

10

IDT70914S

High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM

Commercial Temperature Range

Functional Description

The IDT70914 provides a true synchronous Dual-Port Static RAM

interface.Registeredinputsprovideveryshortset-upandholdtimeson

address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked

ontherisingedgeoftheclock signal.Anasynchronousoutputenableis

provided to ease asynchronous bus interfacing.

The internal write pulse width is dependent on the LOW to HIGH

transitionsoftheclocksignalallowingtheshortestpossiblerealizedcycle

times.Clockenableinputsareprovidedtostalltheoperationoftheaddress

and data input registers without introducing clock skew for very fast

interleavedmemoryapplications.

A HIGH on the CE input for one clock cycle will power down the

internalcircuitrytoreducestaticpowerconsumption.

NOTES:

1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW

voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change

3. ControlsignalsareinitiatedandterminatedontherisingedgeoftheCLK,dependingontheirinputlevel.WhenR/WandCEareLOW,awritecycleisinitiatedontheLOW-to-HIGHtransition

oftheCLK.TerminationofawritecycleisdoneonthenextLOW-to-HIGHtransitionoftheCLK.

4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN.

Mode

Inputs

Register Inputs

ADDR

DATAIN

ADDR

DATAOUT

Load "1"

↑

LH

H

H

H

Load "0"

↑

LLLLL

Hold (do nothing)

↑

HX

X

NC

NC

X

H

X

X

NC

NC

3490 tbl 10

Inputs

Outputs

Mode

Asynchronous

CLK

CE

R/W

OE

↑

H

X

X

High-Z

Deselected, Power-Down

↑

LL

X

Selected and Write Enabled

↑

LH

L

Read Selected and Data Output Enable Read

↑

X

X

H

High-Z

Outputs Disabled

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