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MAX1183 Datasheet(PDF) 4 Page - Maxim Integrated Products

Part No. MAX1183
Description  Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1183 Datasheet(HTML) 4 Page - Maxim Integrated Products

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Dual 10-Bit, 40Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3V, OVDD = +2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through
a 10k
Ω resistor, VIN = 2Vp-p (differential with respect to COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
CLK
0.8 x
VDD
Input High Threshold
VIH
PD, OE, SLEEP, T/B
0.8 x
OVDD
V
CLK
0.2 x
VDD
Input Low Threshold
VIL
PD, OE, SLEEP, T/B
0.2 x
OVDD
V
Input Hysteresis
VHYST
0.1
V
IIH
VIH = OVDD or VDD (CLK)
±5
Input Leakage
IIL
VIL = 0
±5
µA
Input Capacitance
CIN
5pF
DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)
Output Voltage Low
VOL
ISINK = -200µA
0.2
V
Output Voltage High
VOH
ISOURCE = 200µA
OVDD
- 0.2
V
Three-State Leakage Current
ILEAK
OE = OVDD
±10
µA
Three-State Leakage
Capacitance
COUT
OE = OVDD
5pF
POWER REQUIREMENTS
Analog Supply Voltage Range
VDD
2.7
3
3.6
V
Output Supply Voltage Range
OVDD
1.7
2.5
3.6
V
Operating, fINA or B = 20MHz at -0.5dB FS
40
60
Sleep mode
2.8
mA
Analog Supply Current
IVDD
Shutdown, clock idle, PD = OE = OVDD
115
µA
Operating, CL = 15pF,
fINA or B = 20MHz at -0.5dB FS
5.8
mA
Sleep mode
100
Output Supply Current
IOVDD
Shutdown, clock idle, PD = OE = OVDD
210
µA
Operating, fINA or B = 20MHz at -0.5dB FS
120
180
Sleep mode
8.4
mW
Power Dissipation
PDISS
Shutdown, clock idle, PD = OE = OVDD
345
µW
Offset
±0.2
mV/V
Power-Supply Rejection
PSRR
Gain
±0.1
%V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
tDO
Figure 3 (Note 3)
5
8
ns
Output Enable Time
tENABLE
Figure 4
10
ns
Output Disable Time
tDISABLE
Figure 4
1.5
ns


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