Specifications ispLSI 1048E

6

External Timing Parameters

Over Recommended Operating Conditions

UNITS

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

Table 2-0030B/1048E

1

4

3

1

tsu2 + tco1

(

)

-50

MIN. MAX.

DESCRIPTION

#

2

PARAMETER

A

1

Data Propagation Delay, 4PT Bypass, ORP Bypass

–

20.0

ns

A

2

Data Propagation Delay, Worst Case Path

–

ns

A

3

Clock Frequency with Internal Feedback

50.0

–

MHz

–

4

Clock Frequency with External Feedback

–

MHz

–

5

Clock Frequency, Max. Toggle

–

MHz

–

6

GLB Reg. Setup Time before Clock,4 PT Bypass

–

ns

A

7

GLB Reg. Clock to Output Delay, ORP Bypass

–

ns

–

8

GLB Reg. Hold Time after Clock, 4 PT Bypass

–

ns

–

9

GLB Reg. Setup Time before Clock

–

ns

–

10

GLB Reg. Clock to Output Delay

–

ns

–

11

GLB Reg. Hold Time after Clock

–

ns

A

12

Ext. Reset Pin to Output Delay

–

ns

–

13

Ext. Reset Pulse Duration

–

ns

B

14

Input to Output Enable

–

ns

C

15

Input to Output Disable

–

ns

–

18

External Synchronous Clock Pulse Duration, High

6.5

ns

–

19

External Synchronous Clock Pulse Duration, Low

6.5

ns

–

20

I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)

–

ns

–

21

I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

–

ns

42.0

77.0

12.0

0.0

14.5

0.0

13.0

6.5

0.0

24.5

9.5

12.0

20.5

24.0

24.0

–

–

(

)

1

twh + twl

B

16

Global OE Output Enable

–

ns

16.0

C

17

Global OE Output Disable

–

ns

16.0

-70

MIN. MAX.

–

15.0

–

70.0

–

–

–

–

–

–

–

–

–

–

–

–

–

5.0

5.0

–

–

56.0

100.0

9.0

0.0

11.0

0.0

10.0

4.0

0.0

18.5

7.0

9.0

15.0

18.0

18.0

–

–

–

12.0

–

12.0