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AK4633EN Datasheet(PDF) 78 Page - Asahi Kasei Microsystems |
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AK4633EN Datasheet(HTML) 78 Page - Asahi Kasei Microsystems |
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78 / 83 page  [AK4633] MS0447-E-06 2015/10 - 78 - ■ Stop of Clock Master clock can be stopped when ADC, DAC and programmable filters are not in operation. 1. PLL Master Mode External MCKI PMPLL bit (Addr:01H, D0) MCKO bit (Addr:01H, D1) Input (3) (1) (2) "H" or "L" Example: Audio I/F Format: DSP Mode, BCKP = MSBS = “0” BICK frequency at Master Mode : 64fs Input Master Clock Select at PLL Mode : 11.2896MHz Sampling Frequency:8kHz Stop an external MCKI (1) (2) Addr:01H, Data:08H Figure 57. Clock Stopping Sequence (1) <Example> (1) Power down PLL: PMPLL bit = “1” “0” (2) Stop MCKO clock: MCKO bit = “1” “0” (3) Stop an external master clock. 2. PLL Slave Mode (FCK or BICK pins) External BICK PMPLL bit (Addr: 01H,D0 ) Input (1 ) (2 ) External FCK Input (2 ) Example : Audio I/F Format : DSP Mode, BCKP = MSBS = “0” PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz (1) Addr:01H, Data:04H (2) Stop the external clocks Figure 58. Clock Stopping Sequence (2) <Example> (1) Power down PLL: PMPLL bit = “1” “0” (2) Stop the external BICK and FCK clocks. |
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