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AK4633EN Datasheet(PDF) 53 Page - Asahi Kasei Microsystems |
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AK4633EN Datasheet(HTML) 53 Page - Asahi Kasei Microsystems |
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53 / 83 page  [AK4633] MS0447-E-06 2015/10 - 53 - <Control Sequence of Speaker Amp> Speaker-Amp can be powered-up/down by controlling the PMSPK bit. When the PMSPK bit is “0”, the SPP and SPN pins are placed in a Hi-Z state. When the PMSPK bit is “1” and SPPSN bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. When the PMSPK bit is “1” and the PDN pin is controlled from “L” to “H”, the SPP and SPN pins rise up from power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. Because the SPP and SPN pins rise up at power-save-mode, this mode can reduce pop noise. When the AK4633 is powered-down, pop noise can be also reduced by first entering power-save-mode. PMSPKbit SPPSNbit SPPpin SPNpin SVDD/2 SVDD/2 Hi-Z Hi-Z Hi-Z Hi-Z >t1(Note) >0 (Note) SPPSN bit should be set to “1” at more than 1ms after PMSPK bit is set to “1”. When BEEP Input Amp and Speaker Amp are powered-up at the same time, SPPSN bit should be set to “1” after BEEP Input become stable. When the resistance and capacitance of BEEP pin are R=20k and C=0.1F, 10ms(=5) is required for BEEP Input to become stable. Figure 42. Power-up/Power-down Timing for Speaker-Amp |
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