HY62SF16101C Series

Rev.04 /Mar. 02

6

WRITE CYCLE 1(1,4,8) (/WE Controlled)

WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled)

Notes:

1. A write occurs during the overlap of a low /WE, a low /CS1 and low /UB and/or /LB.

2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the

output must not be applied.

4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the

/WE transition, outputs remain in a high impedance state.

5. Q(data out) is the same phase with the write data of this write cycle.

6. Q(data out) is the read data of the next address.

7. Transition is measured +200mV from steady state.

This parameter is sampled and not 100% tested.

8. /CS in high for the standby, low for active

/UB and /LB in high for the standby, low for active

Data Valid

ADDR

Data

Out

/CS

/UB,/LB

/WE

tWC

tCW

tBW

tAW

tWP

Data In

High-Z

tAS

tDW

tDH

tOW

(5)

(6)

Data Valid

ADDR

Data

Out

/CS

/UB,/LB

/WE

tWC

tCW

tBW

tAW

tWP

Data In

tDW

tDH

High-Z

High-Z

tAS