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IDT723626 Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT723626 Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 35 page  7 IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2 COMMERCIAL TEMPERATURE RANGE DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723626/723636/723646 with CLKA, CLKB and CLKC set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnectedtonormalizethegraphtoazerocapacitanceload.Oncethecapacitanceloadperdata-outputchannelandthenumberofIDT723626/723636/ 723646 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. CALCULATING POWER DISSIPATION With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by: PT = VCC x [ICC(f) + (N x ΔICC x dc)] + Σ(CL x VCC2 X fo) N where: N = number of inputs driven by TTL levels ΔICC = increase in power supply current for each input at a TTL HIGH level dc = duty cycle of inputs at a TTL HIGH level of 3.4V CL = output capacitance load fo = switchingfrequencyofanoutput Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS) 010 20 30 40 50 60 70 0 50 100 250 300 VCC = 5.5V 3271 drw02a 200 150 80 90 VCC = 4.5V VCC = 5.0V fdata = 1/2 fS TA = 25 °C CL = 0 pF fS ⎯ Clock Frequency ⎯ MHz |
Similar Part No. - IDT723626_14 |
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Similar Description - IDT723626_14 |
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