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IDT70121S Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT70121S Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 16 page 9 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) R/ W tWC tHZ tAW tHZ tAS tWP DATAOUT tDW tDH tOW OE ADDRESS DATAIN CE tWZ (4) (4) tWR 2654 drw 07 (3) (7) (2) (6) (7) (7) CE tWC tAS tWR tDW tDH ADDRESS DATAIN R/ W tAW tEW 2654 drw 08 (6) (2) (3) |
Similar Part No. - IDT70121S_14 |
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Similar Description - IDT70121S_14 |
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