9

IDT70121/IDT70125

High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt

Industrial and Commercial Temperature Ranges

NOTES:

1. R/W or CE must be HIGH during all address transitions.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

R/

W

OE

ADDRESS

CE

(4)

(4)

2654 drw 07

(3)

(7)

(2)

(6)

(7)

(7)

CE

ADDRESS

R/

W

2654 drw 08

(6)

(2)

(3)