6

IDT7038L

High-Speed 64K x 18 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing of Power-Up Power-Down

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.

has no relation to valid output data.

6. Refer to Chip Enable Truth Table.

AC Test Conditions

Figure 2. Output Test Load

* Including scope and jig.

Figure 1. AC Output Test Load

4837 drw 04

893

Ω

30pF

347

Ω

5V

BUSY

INT

893

Ω

5pF*

347

Ω

5V

4837 drw 03

.

R/

W

CE

ADDR

OE

UB, LB

4837 drw 05

(4)

(4)

(4)

(4)

(1)

(2)

(3,4)

VALID DATA

(4)

(6)

CE

4837 drw 06

(6)

50%

50%

.

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns Max.

1.5V

1.5V

Figures 1 and 2

4837 tbl 11